Professor in Computer Science and Engineering and Electrical Engineering at Pennsylvania State University, U.S.A.

Brief Biography:
Prof. Vijaykrishnan Narayanan is a Professor of Computer Science and Engineering and Electrical Engineering at The Pennsylvania State University. He is a Fellow of IEEE and the Editor-in-Chief of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. He also served as the founding co-Editor-in-Chief of the ACM Journal of Emerging Technologies in Computer Systems.

Professor in Electronics Engineering (VLSI Design and Education Center) at University of Tokyo, Japan

Brief Biography:
Prof. Masahiro Fujita received his Ph.D. in Information Engineering from the University of Tokyo in 1985 on his work on model checking of hardware designs by using logic programming languages. In 1985, he joined Fujitsu as a researcher and started to work on hardware automatic synthesis as well as formal verification methods and tools, including enhancements of BDD/SAT-based techniques. From 1993 to 2000, he was director at Fujitsu Laboratories of America and headed a hardware formal verification group developing a formal verifier for real-life designs having more than several million gates. The developed tool has been used in production internally at Fujitsu and externally as well. Since March 2000, he has been a professor at VLSI Design and Education Center of the University of Tokyo. He has done innovative work in the areas of hardware verification, synthesis, testing, and software verification-mostly targeting embedded software and web-based programs. He has been involved in a Japanese governmental research project for dependable system designs and has developed a formal verifier for C programs that could be used for both hardware and embedded software designs. The tool is now under evaluation jointly with industry under governmental support. He has authored and co-authored 10 books, and has more than 200 publications. He has been involved as program and steering committee member in many prestigious conferences on CAD, VLSI designs, software engineering, and more. His current research interests include synthesis and verification in SoC (System on Chip), hardware/software co-designs targeting embedded systems, digital/analog co-designs, and formal analysis, verification, and synthesis of web-based programs and embedded programs.

Scientist (G) in Department of Electronics and Information Technology at MIT, Govt. of India

Professor in Computer Science and Engineering at Indian Institute of Technology, Delhi

Brief Biography:
Prof. M. Balakrishnan is a Professor in the Department of Computer Science & Engineering at I.I.T. Delhi. He obtained his B.E.(Hons.) in Electronics & Electrical Engg. from BITS Pilani in 1977 and Ph.D. from EE Dept. IIT Delhi in 1985. He worked as a Scientist in CARE, IIT Delhi from 1977 to 1985 where he was involved in designing and implementing real-time DSP systems. For the last 27 years, he is involved in teaching and research in the areas of digital systems design, electronic design automation and embedded systems. He has supervised 9 Ph.D. students, 3 MSR students, 160 M.Tech/B.Tech projects and published nearly 98 conference and journal papers. Further, he has held visiting positions in universities in Canada, USA and Germany. At IIT Delhi, he has been the Philips Chair Professor, Head of the Department of Computer Science & Engineering, Dean of Post Graduate Studies & Research at IIT Delhi and Deputy Director (Faculty) at IIT Delhi. He has been associated with a number of initiatives to promote research at IIT Delhi. Apart from conducting research in the areas of Low power design as well as hardware-software co-design, his focus is on developing a number of embedded assistive devices for the mobility and education of visually impaired.

Research & Development Head in Digital Networking Product Division at Freescale Semiconductor, India

Brief Biography:
Mr.Parvez Zaman is currently the R&D Head of Digital Networking Product Division at Freescale Semiconductor India. He obtained his M.Sc in Electronics Science from University of Kolkata in 1993 and M.Tech in Electrical Engineering from IIT, Bombay in 1998. He has 18+ years of experience in Research, Leadership and Execution in SoC design, circuit design, and intellectual property with Freescale Semiconductor and also worked as a CSIR Fellow. During his industry tenure, he involved in leading and designing high performance multi-core SoCs in cutting edge technology, validation and enablement of these devices, circuit design, high speed IO Design, power optimization and technology Interface. He is also an active member in Industry-Academia consortium and the Vice Chair of IEEE SSCS Delhi Chapter.

Senior Scientist in IC Design Group at CSIR-Central Electronics Engineering Research Institute- Pilani, India

Senior Manager Research & Development at Synopsys, India

Brief Biography:
Mr. Ashwani Aggarwal is working as Senior Manager, R&D for Platform Architect – Multi Core Optimization (PA-MCO) product at Synopsys . Ashwani completed his Masters in Electronics & Communication from Delhi Technological University (formerly, DCE) in 1999. Ashwani has work experience in design and development in ESL, EDA, embedded and telecommunication domains. He is managing the team involved in the creation of SystemC TLM models for Processors, Interconnects and Peripherals. In addition, he has been leading the effort in defining and developing the solutions for System Level Power analysis and workload model creations.

Senior CAD Engineer at STMicroelectronics ,India Limited

Brief Biography:
Mr. Atul has nearly 11 years of experience with STMicroelectronics and has served in various capacities to enable CAD tools and methodologies for IP developments at ST. He has been instrumental in working with technologies like 3D parasitic extraction, memory scrambling, DFM, electro migration & IR drop and transistor level simulations. He has several publications on these topics at various conference on these topics. Recently he has been working on topics of reliability and will be talking about full custom layouts and reliability in the same context today.